Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and time (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow relative timing to simplify AES realization Field-Programmable-Gate-Array (FPGA). Second, optimize completion detection circuits therein achieve low power/overhead solution. Third, randomized delay-line control data-propagation amplify countermeasures for our accelerator. Fourth, validate based on two commercially-available Sakura-X Arty-A7 FPGA boards. Fifth, comprehensively evaluate 74 attacking models these boards, compare results against benchmarking synchronous-logic (sync-logic). show that is unbreakable within 1 million electromagnetic (EM) traces where sync-logic counterpart breakable <; 30K EM traces. To best knowledge, first evaluated at first/last round, various locations (i.e. before/after Substitute-Box), Hamming weight/distance, bit model, zero-model of SCAs.